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M.Tech VLSI

IEEE 2016-17 Projects on VLSI Design

Code Project Title Year Downloads Downloads Cryptography
16V01 High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels IEEE 2016
16V02 Design of low power, high performance 2-4 and 4-16 mixed-logic line decoders IEEE 2016
16V03 Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder IEEE 2016
16V04 Design of reversible 32-bit BCD add-subtract unit using parallel pipelined method IEEE 2016
16V05 Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder IEEE 2015
15V26 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic IEEE 2015
15V27 Design and Analysis of Approximate Compressors for Multiplication IEEE 2015
15V28 Recursive Approach to the Design of a Parallel Self-Timed Adder IEEE 2015
15V29 High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels IEEE 2015
15V30 High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter IEEE 2015
15V31 Implementation of high performance SRAM Cell Using Transmission Gate IEEE 2015
16V06 Low power reconfigurable Hilbert transformer design with row bypassing multiplier on FPGA IEEE 2016 Cryptography
16V07 A novel power efficient N-MOS based 1-bit full adder IEEE 2016
16V08 Low power 8-bit ALU design using full adder and multiplexer IEEE 2016
16V09 A novel power efficient pulse triggered flip-flop with minimum transistors IEEE 2016
16V10 Modeling of adders using CMOS and GDI logic for multiplier applications IEEE 2016
16V11 Low power high speed area efficient error tolerant adder using gate diffusion input method IEEE 2016
16V12 Ultra low voltage synthesizable memories: a trade-off discussion in 65 nm CMOS IEEE 2016
15V15 Low-Power and Area-Efficient Shift Register Using Pulsed Latches IEEE 2015
15V17 A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications IEEE 2015
15V19 Low power Multiplier Architectures using Vedic Mathematics in 45 nm Technology for High Speed Computing IEEE 2015
15V20 Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer IEEE 2015
15V21 Design of a Power Optimal Reversible FIR Filter for Speech Signal Processing IEEE 2015
15V23 Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder IEEE 2015
15V32 Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology IEEE 2015 Cryptography
15V33 Ultralow-Energy Variation-Aware Design: Adder Architecture Study IEEE 2015
15V34 All Optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential Counters IEEE 2015
15V35 Design of Full Adder circuit using Double Gate MOSFET IEEE 2015
15V36 Design of Optimized Reversible Binary and BCD Adders IEEE 2015
15V37 A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell IEEE 2015
15V38 Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits IEEE 2015
15V39 Modeling CMOS Gates Using Equivalent Inverters IEEE 2015
15V40 Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm IEEE 2015
15V42 Variable Latency Speculative Han-Carlson Adder IEEE 2015
16V13 Design of an optimized reversible bidirectional barrel shifter IEEE 2016 Cryptography
16V14 Encryption using reconfigurable reversible logic gate IEEE 2016
16V15 A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6t bit cell enabling logic-in-memory IEEE 2016
16V16 Design of register file using reversible logic IEEE 2016
16V17 A heuristic for linear nearest neighbor realization of quantum circuits by SWAP gate insertion using -gate look ahead IEEE 2016
16V18 A parallel decimal multiplier using hybrid binary coded decimal IEEE 2016
15V07 Implementation of Testable Reversible Sequential Circuit on FPGA IEEE 2015
15V09 A Novel Realization of Reversible LFSR for its Application in Cryptography IEEE 2015
15V11 IC Layout Design of Decoder Using Electric VLSI Design IEEE 2015
15V12 Low-Complexity Tree Architecture for Finding the First Two Minima IEEE 2015
15V13 Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits IEEE 2015
15V14 Synthesis of Balanced Quaternary Reversible Logic Circuit IEEE 2015
16V19 A modified partial product generator for redundant binary multipliers IEEE 2016 DSP & DIP Applications
16V20 A modified partial product generator for redundant binary multipliers IEEE 2016
16V21 Pre-encoded multipliers based on non-redundant radix-4 signed-digit encoding IEEE 2016
16V22 Floating-point butterfly architecture based on binary signed-digit representation IEEE 2016
16V23 Low-quantum cost circuit constructions for adder and symmetric Boolean functions IEEE 2016
16V24 A high-performance fir filter architecture for fixed and reconfigurable applications IEEE 2016
16V25 Energy-aware scheduling of FIR filter structures using a timed automata model IEEE 2016
15V52 A 32 BIT MAC Unit Design Using Vedic Multiplier and Reversible Logic Gate IEEE 2015
15V53 Towards reversible QCA computers: reversible gates and ALU IEEE 2015
15V54 Design And Development of Efficient Reversible Floating Point Arithmetic unit IEEE 2015
15V56 Parallel Prefix Modulo Adder via Double Representation of Residues in [0, 2] IEEE 2015
15V57 Design And Implementation Of Field Programmable Gate Array Based Error Tolerant Adder For Image Processing Application IEEE 2015
15V58 Design and Implementation of Arithmetic Logic Unit (ALU) using Modified Novel Bit Adder in QCA IEEE 2015
15V59 Quantum Cost Realization of New Reversible Gates with Transformation Based Synthesis Technique IEEE 2015
15V60 Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming IEEE 2015
16V26 Design of reversible circuits with high testability IEEE 2016 DSP & DIP Applications
16V27 An improved design of a reversible fault tolerant LUT-based FPGA IEEE 2016
16V28 FTCAM: An area-efficient flash-based ternary CAM design IEEE 2016
16V29 Logic synthesis in reversible PLA IEEE 2016
16V30 Design for testability of sleep convention logic IEEE 2016
16V31 Synthesis of approximate coders for on-chip interconnects using reversible logic IEEE 2016
16V32 Fault detection in parity preserving reversible circuits IEEE 2016
15V43 Index-based Round-Robin Arbiter for NOC Routers IEEE 2015
15V44 An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC IEEE 2015
15V45 A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic IEEE 2015
15V46 A novel design of reversible 2:4 decoder IEEE 2015
15V47 Design and Implementation of a Reversible Central Processing Unit IEEE 2015
15V48 Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers IEEE 2015
15V50 Logic Debugging of Arithmetic Circuits IEEE 2015
15V51 Reversible logic based mapping of quaternary sequential circuits using QGFSOP expression IEEE 2015
16V33 Design of reversible circuits with high testability IEEE 2016 Reversible Logic
16V34 Squaring in reversible logic using zero garbage and reduced ancillary inputs IEEE 2016
16V35 A pre-optimization technique to generate initial reversible circuits with low quantum cost IEEE 2016
16V36 Primitive components of reversible logic synthesis IEEE 2016
16V37 Reversible circuit synthesis using binary decision diagrams IEEE 2016
16V38 An efficient approach to design a compact reversible programmable logic array IEEE 2016
16V39 Re-writing HDL descriptions for line-aware synthesis of reversible circuits IEEE 2016
16V40 Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking IEEE 2016
15V01 Design of priority encoding based reversible comparators IEEE 2015
15V02 On the Analysis of Reversible Booth’s Multiplier IEEE 2015
15V03 Berger check and fault tolerant reversible arithmetic component design IEEE 2015
15V04 Parity Preserving Adder/Subtractor Using a Novel Reversible Gate IEEE 2015
15V05 Online Testing for Three Fault Models in Reversible Circuits IEEE 2015
15V06 A New Gate for Low Cost Design of All-optical Reversible Logic Circuit IEEE 2015
WYV62 Design and Estimation of delay, power and area for Parallel prefix adders IEEE 2014 Area Efficient  &Low Power
WYV68 Approach to design a compact reversible low power binary comparator IEEE 2014
WYV65 Area–Delay–Power Efficient Carry-Select Adder IEEE 2014
WYV55 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor IEEE 2013
WYV61 Low power and area efficient carry select adder 2014
WYV37 Architectural level power optimization techniques for multipliers 2014
WYV56 Design of high speed hybrid carry select adder IEEE 2014 Less Delay & High Speed VLSI
WYV57 Optimized Reversible Vedic Multipliers for High Speed Low Power operations IEEE 2014
WYV2 Radix-8 booth encoded modulo multipliers with adoptive delay for high dynamic range Residue Number System. IEEE
WYV4 Design of characterization of parallel pre-fix adders using FPGA. IEEE
WYV7 Reducing the computation time in (short bit-width) two’s complement multipliers. IEEE
WYV9 Based on radix-2 modified booth algorithm a new VLSI architecture of parallel multiplier accumulator IEEE
WYV36 The design of high performance barrel integer adder 2014
WYV54 A high speed binary floating point multiplier using Dadda algorithm IEEE 2014
WYV63 Detection of hardware Trojan in SEA using path delay IEEE 2014
WYV66 Detection of hardware Trojan in SEA using path delay IEEE 2014
WYV8 FPGA implementation of scalable encryption algorithm IEEE Data hiding
WYV15 FPGA implementation of SHA-1 algorithm IEEE
WYV12 Implementation of the hummingbird cryptographic algorithm IEEE
WYV35 Cyclic redundancy check generation using multiple lookup table algorithms IEEE
WYV1 FPGA implementation of scalable encryption algorithm IEEE Communication  Systems
WYV5 Self-immunity technique to improve register file integrity against soft errors IEEE
WYV6 Design and simulation of UART serial communication module based on VHDL IEEE
WYV11 Hardware implementation of RFID mutual authentication protocol IEEE
WYV13 Verilog modeling of WI-FI MAC layer for transmitter IEEE
WYV14 FPGA implementation of USB transceiver macro cell interface with usb2.0 specifications IEEE
WYV17 VHDL implementation of lossless data compression IEEE
WYV18 A VLIW vector media compressor with cascaded SIMD ALU’S IEEE
WYV21 Design and implementation of blue tooth security using VHDL IEEE
WYV48 Design and implementation of APB bridge based on AMBA 4.0 IEEE
WYV50 Applying CDMA technique to network-on-chip IEEE 2014
WYV22 Implementation of vending machine controller IEEE Communication  Systems
WYV23 Implementation of traffic light controller IEEE
WYV24 Implementation of digital clock IEEE
WYV25 Implementation of electronic voting machine controller IEEE
WYV26 Implementation of universal asynchronous receiver/transmitter IEEE
WYV27 Implementation of serial peripheral interface IEEE
WYV28 Implementation of content addressable memory IEEE
WYV29 Implementation of 32 bit cyclic redundancy check IEEE
WYV30 Implementation of barrel shifter IEEE
WYV31 Implementation of round robin arbiter IEEE
WYV34 Finite state machine based vending machine controller with auto-billing features IEEE
WYV3 High throughput da-based DCT with high accuracy error compensated adder tree. IEEE Communication  Systems
WYV64 Parallel multiplier accumulator based on radix-2 modified booth algorithm by using a VLSI architecture IEEE 2014
WYV10 LUT optimization for memory-based computation. IEEE
WYV33 Optimized implementation of FFT processor for OFDM systems IEEE
WYV39 Arithmetic & logic unit (ALU) design using reversible control IEEE Digital signal processing applications
WYV38 Design and minimization of reversible circuits for a data acquisition and storage system IEEE
WYV41 Design & implementation of mac unit using reversible logic IEEE
WYV44 An efficient implementation of floating point multiplier IEEE
WYV49 A table-based algorithm for pipelined CRC calculation IEEE
WYV69 Parity preserving logic based fault tolerant reversible ALU IEEE 2014
WYV32 A novel analysis of sequential circuits design using reversible logic gates IEEE Reversible Logic Gates based implementations
WYV40 A distinguish between reversible and conventional logic gates IEEE
WYV42 Modified Toffoli gate and its applications in designing components of reversible arithmetic and logic unit IEEE
WYV43 A new reversible design of BCD adder IEEE
WYV45 Fault tolerant variable block carry skip logic (VBCSL) using parity preserving IEEE
WYV46 Design of a nanometric reversible 4-bit binary counter with parallel load IEEE
WYV47 Introduction to reversible logic gates & its application IEEE
WYV51 Realization of 2:4 reversible decoder and its applications IEEE 2014
WYV52 All optical reversible multiplexer design using Mach-Zehnder interferometer IEEE 2014
WYV53 Design of dedicated reversible quantum circuitry for square computation IEEE 2014
WYV58 Energy efficient code converters using reversible logic gates IEEE 2014
WYV59 Design of low logical cost conservative reversible adders using novel PCTG IEEE 2014
WYV60 Contemplation of synchronous gray code counter and its variants using reversible logic gates IEEE 2014
WYV67 An optimized design of binary comparator circuit in quantum computing IEEE 2014
WYV70 ASIC design of reversible multiplier circuit IEEE 2014
WYV71 A low energy and high performance dm^2 adder IEEE 2014 Low power, Low Voltage &High speed
WYV72 Analysis and design of a low-voltage low-power double-tail comparator IEEE 2014
WYV73 Low power pulse triggered flip-flop design based on signal feed-through scheme IEEE 2014
WYV74 Increase in read noise margin of single-bit-line SRAM using adiabatic change of word line voltage IEEE 2014
WYV75 An 8t low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FINFETS IEEE 2014
WYV76 Low power noise tolerant domino 1-bit full adder IEEE 2014
WYV77 A novel low leakage and high density 5t CMOS SRAM cell in 45nm technology IEEE 2014
WYV78 A new design of low power high speed hybrid CMOS full adder IEEE 2014
WYV79 A low energy and high performance dm^2 adder IEEE 2014 Low power Voltage &High speed
WYV80 A sub-threshold eight transistor (8T) SRAM cell design for stability improvement IEEE 2014
WYV81 An arithmetic and logic unit optimized for area and power IEEE 2014
15V61 Design of high performance multiply-accumulate computation unit IEEE 2015
15V62 Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit IEEE 2015
15V63 An approach to design a multiplexer based module of a novel reversible gate for FPGA architecture IEEE 2015
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