Code |
Project Title
| Year |
Downloads
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Downloads
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16V01 |
High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels |
IEEE 2016 |
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16V02 |
Design of low power, high performance 2-4 and 4-16 mixed-logic line decoders |
IEEE 2016 |
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16V03 |
Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder |
IEEE 2016 |
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16V04 |
Design of reversible 32-bit BCD add-subtract unit using parallel pipelined method |
IEEE 2016 |
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16V05 |
Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder |
IEEE 2015 |
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15V26 |
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic |
IEEE 2015 |
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15V27 |
Design and Analysis of Approximate Compressors for Multiplication |
IEEE 2015 |
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15V28 |
Recursive Approach to the Design of a Parallel Self-Timed Adder |
IEEE 2015 |
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15V29 |
High-speed and energy-efficient carry skip adder operating under a wide range of supply voltage levels |
IEEE 2015 |
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15V30 |
High-Speed, Modified, Bulk stimulated, Ultra-Low-Voltage, Domino Inverter |
IEEE 2015 |
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15V31 |
Implementation of high performance SRAM Cell Using Transmission Gate |
IEEE 2015 |
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16V06 |
Low power reconfigurable Hilbert transformer design with row bypassing multiplier on FPGA |
IEEE 2016 |
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16V07 |
A novel power efficient N-MOS based 1-bit full adder |
IEEE 2016 |
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16V08 |
Low power 8-bit ALU design using full adder and multiplexer |
IEEE 2016 |
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16V09 |
A novel power efficient pulse triggered flip-flop with minimum transistors |
IEEE 2016 |
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16V10 |
Modeling of adders using CMOS and GDI logic for multiplier applications |
IEEE 2016 |
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16V11 |
Low power high speed area efficient error tolerant adder using gate diffusion input method |
IEEE 2016 |
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16V12 |
Ultra low voltage synthesizable memories: a trade-off discussion in 65 nm CMOS |
IEEE 2016 |
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15V15 |
Low-Power and Area-Efficient Shift Register Using Pulsed Latches |
IEEE 2015 |
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15V17 |
A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications |
IEEE 2015 |
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15V19 |
Low power Multiplier Architectures using Vedic Mathematics in 45 nm Technology for High Speed Computing |
IEEE 2015 |
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15V20 |
Design & Study of a Low Power High Speed Full Adder Using GDI Multiplexer |
IEEE 2015 |
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15V21 |
Design of a Power Optimal Reversible FIR Filter for Speech Signal Processing |
IEEE 2015 |
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15V23 |
Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder |
IEEE 2015 |
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15V32 |
Energy and Area Efficient Three-Input XOR/XNORs With
Systematic Cell Design Methodology
|
IEEE 2015 |
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15V33 |
Ultralow-Energy Variation-Aware Design: Adder Architecture Study |
IEEE 2015 |
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15V34 |
All Optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential Counters |
IEEE 2015 |
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15V35 |
Design of Full Adder circuit using Double Gate MOSFET |
IEEE 2015 |
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15V36 |
Design of Optimized Reversible Binary and BCD Adders |
IEEE 2015 |
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15V37 |
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell |
IEEE 2015 |
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15V38 |
Using Boolean Tests to Improve Detection of Transistor Stuck-open Faults in CMOS Digital Logic Circuits |
IEEE 2015 |
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15V39 |
Modeling CMOS Gates Using Equivalent Inverters |
IEEE 2015 |
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15V40 |
Reducing RMS Noise in CMOS dynamic reconfigurable latched comparator in 50 nm |
IEEE 2015 |
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15V42 |
Variable Latency Speculative Han-Carlson Adder |
IEEE 2015 |
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16V13 |
Design of an optimized reversible bidirectional barrel shifter
|
IEEE 2016 |
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16V14 |
Encryption using reconfigurable reversible logic gate |
IEEE 2016 |
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16V15 |
A 28 nm configurable memory (TCAM/BCAM/SRAM) using push-rule 6t bit cell enabling logic-in-memory |
IEEE 2016 |
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16V16 |
Design of register file using reversible logic |
IEEE 2016 |
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16V17 |
A heuristic for linear nearest neighbor realization of quantum circuits by SWAP gate insertion using -gate look ahead |
IEEE 2016 |
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16V18 |
A parallel decimal multiplier using hybrid binary coded decimal |
IEEE 2016 |
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15V07 |
Implementation of Testable Reversible Sequential Circuit on FPGA |
IEEE 2015 |
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15V09 |
A Novel Realization of Reversible LFSR for its Application in Cryptography |
IEEE 2015 |
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15V11 |
IC Layout Design of Decoder Using Electric VLSI Design |
IEEE 2015 |
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15V12 |
Low-Complexity Tree Architecture for Finding the First Two Minima |
IEEE 2015 |
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15V13 |
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits |
IEEE 2015 |
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15V14 |
Synthesis of Balanced Quaternary Reversible Logic Circuit |
IEEE 2015 |
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16V19 |
A modified partial product generator for redundant binary multipliers
|
IEEE 2016 |
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16V20 |
A modified partial product generator for redundant binary multipliers
|
IEEE 2016 |
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16V21 |
Pre-encoded multipliers based on non-redundant radix-4 signed-digit encoding
|
IEEE 2016 |
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16V22 |
Floating-point butterfly architecture based on binary signed-digit representation
|
IEEE 2016 |
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16V23 |
Low-quantum cost circuit constructions for adder and symmetric Boolean functions
|
IEEE 2016 |
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16V24 |
A high-performance fir filter architecture for fixed and reconfigurable applications
|
IEEE 2016 |
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16V25 |
Energy-aware scheduling of FIR filter structures using a timed automata model
|
IEEE 2016 |
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15V52 |
A 32 BIT MAC Unit Design Using Vedic Multiplier and Reversible Logic Gate |
IEEE 2015 |
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15V53 |
Towards reversible QCA computers: reversible gates and ALU |
IEEE 2015 |
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15V54 |
Design And Development of Efficient Reversible Floating Point Arithmetic unit |
IEEE 2015 |
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15V56 |
Parallel Prefix Modulo Adder via Double Representation of Residues in [0, 2] |
IEEE 2015 |
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15V57 |
Design And Implementation Of Field Programmable Gate Array Based Error Tolerant Adder For Image Processing Application |
IEEE 2015 |
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15V58 |
Design and Implementation of Arithmetic Logic Unit (ALU) using Modified Novel Bit Adder in QCA |
IEEE 2015 |
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15V59 |
Quantum Cost Realization of New Reversible Gates
with Transformation Based Synthesis Technique
|
IEEE 2015 |
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15V60 |
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming |
IEEE 2015 |
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16V26 |
Design of reversible circuits with high testability
|
IEEE 2016 |
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16V27 |
An improved design of a reversible fault tolerant LUT-based FPGA
|
IEEE 2016 |
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16V28 |
FTCAM: An area-efficient flash-based ternary CAM design
|
IEEE 2016 |
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16V29 |
Logic synthesis in reversible PLA
|
IEEE 2016 |
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16V30 |
Design for testability of sleep convention logic
|
IEEE 2016 |
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16V31 |
Synthesis of approximate coders for on-chip interconnects using reversible logic
|
IEEE 2016 |
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16V32 |
Fault detection in parity preserving reversible circuits
|
IEEE 2016 |
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15V43 |
Index-based Round-Robin Arbiter for NOC Routers |
IEEE 2015 |
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15V44 |
An Improved Dynamic Latch Based Comparator for 8-bit Asynchronous SAR ADC |
IEEE 2015 |
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15V45 |
A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic |
IEEE 2015 |
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15V46 |
A novel design of reversible 2:4 decoder |
IEEE 2015 |
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15V47 |
Design and Implementation of a Reversible Central Processing Unit |
IEEE 2015 |
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15V48 |
Performance Comparison of Pass Transistor and CMOS Logic Configuration based De-Multiplexers |
IEEE 2015 |
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15V50 |
Logic Debugging of Arithmetic Circuits |
IEEE 2015 |
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15V51 |
Reversible logic based mapping of quaternary sequential circuits using QGFSOP expression |
IEEE 2015 |
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16V33 |
Design of reversible circuits with high testability
|
IEEE 2016 |
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16V34 |
Squaring in reversible logic using zero garbage and reduced ancillary inputs
|
IEEE 2016 |
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16V35 |
A pre-optimization technique to generate initial reversible circuits with low quantum cost
|
IEEE 2016 |
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16V36 |
Primitive components of reversible logic synthesis
|
IEEE 2016 |
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16V37 |
Reversible circuit synthesis using binary decision diagrams
|
IEEE 2016 |
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16V38 |
An efficient approach to design a compact reversible programmable logic array
|
IEEE 2016 |
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16V39 |
Re-writing HDL descriptions for line-aware synthesis of reversible circuits
|
IEEE 2016 |
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16V40 |
Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking
|
IEEE 2016 |
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15V01 |
Design of priority encoding based reversible comparators |
IEEE 2015 |
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15V02 |
On the Analysis of Reversible Booth’s Multiplier |
IEEE 2015 |
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15V03 |
Berger check and fault tolerant reversible arithmetic component design |
IEEE 2015 |
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15V04 |
Parity Preserving Adder/Subtractor Using a Novel Reversible Gate |
IEEE 2015 |
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15V05 |
Online Testing for Three Fault Models in Reversible Circuits |
IEEE 2015 |
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15V06 |
A New Gate for Low Cost Design of All-optical Reversible Logic Circuit |
IEEE 2015 |
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WYV62 |
Design and Estimation of delay, power and area for Parallel prefix adders |
IEEE 2014 |
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WYV68 |
Approach to design a compact reversible low power binary comparator |
IEEE 2014 |
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WYV65 |
Area–Delay–Power Efficient Carry-Select Adder |
IEEE 2014 |
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WYV55 |
A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor |
IEEE 2013 |
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WYV61 |
Low power and area efficient carry select adder |
2014 |
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WYV37 |
Architectural level power optimization techniques for multipliers |
2014 |
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WYV56 |
Design of high speed hybrid carry select adder |
IEEE 2014 |
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WYV57 |
Optimized Reversible Vedic Multipliers for High Speed Low Power operations |
IEEE 2014 |
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WYV2 |
Radix-8 booth encoded modulo multipliers with adoptive delay for high dynamic range Residue Number System. |
IEEE |
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WYV4 |
Design of characterization of parallel pre-fix adders using FPGA. |
IEEE |
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WYV7 |
Reducing the computation time in (short bit-width) two’s complement multipliers. |
IEEE |
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WYV9 |
Based on radix-2 modified booth algorithm a new VLSI architecture of parallel multiplier accumulator |
IEEE |
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WYV36 |
The design of high performance barrel integer adder |
2014 |
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WYV54 |
A high speed binary floating point multiplier using Dadda algorithm |
IEEE 2014 |
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WYV63 |
Detection of hardware Trojan in SEA using path delay |
IEEE 2014 |
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WYV66 |
Detection of hardware Trojan in SEA using path delay |
IEEE 2014 |
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WYV8 |
FPGA implementation of scalable encryption algorithm |
IEEE |
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WYV15 |
FPGA implementation of SHA-1 algorithm |
IEEE |
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WYV12 |
Implementation of the hummingbird cryptographic algorithm |
IEEE |
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WYV35 |
Cyclic redundancy check generation using multiple lookup table algorithms |
IEEE |
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WYV1 |
FPGA implementation of scalable encryption algorithm |
IEEE |
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WYV5 |
Self-immunity technique to improve register file integrity against soft errors |
IEEE |
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WYV6 |
Design and simulation of UART serial communication module based on VHDL |
IEEE |
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WYV11 |
Hardware implementation of RFID mutual authentication protocol |
IEEE |
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WYV13 |
Verilog modeling of WI-FI MAC layer for transmitter |
IEEE |
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WYV14 |
FPGA implementation of USB transceiver macro cell interface with usb2.0 specifications |
IEEE |
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WYV17 |
VHDL implementation of lossless data compression |
IEEE |
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WYV18 |
A VLIW vector media compressor with cascaded SIMD ALU’S |
IEEE |
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WYV21 |
Design and implementation of blue tooth security using VHDL |
IEEE |
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WYV48 |
Design and implementation of APB bridge based on AMBA 4.0 |
IEEE |
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WYV50 |
Applying CDMA technique to network-on-chip |
IEEE 2014 |
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WYV22 |
Implementation of vending machine controller |
IEEE |
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WYV23 |
Implementation of traffic light controller |
IEEE |
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WYV24 |
Implementation of digital clock |
IEEE |
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WYV25 |
Implementation of electronic voting machine controller |
IEEE |
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WYV26 |
Implementation of universal asynchronous receiver/transmitter |
IEEE |
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WYV27 |
Implementation of serial peripheral interface |
IEEE |
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WYV28 |
Implementation of content addressable memory |
IEEE |
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WYV29 |
Implementation of 32 bit cyclic redundancy check |
IEEE |
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WYV30 |
Implementation of barrel shifter |
IEEE |
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WYV31 |
Implementation of round robin arbiter |
IEEE |
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WYV34 |
Finite state machine based vending machine controller with auto-billing features |
IEEE |
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WYV3 |
High throughput da-based DCT with high accuracy error compensated adder tree. |
IEEE |
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WYV64 |
Parallel multiplier accumulator based on radix-2 modified booth algorithm by using a VLSI architecture |
IEEE 2014 |
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WYV10 |
LUT optimization for memory-based computation. |
IEEE |
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WYV33 |
Optimized implementation of FFT processor for OFDM systems |
IEEE |
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WYV39 |
Arithmetic & logic unit (ALU) design using reversible control |
IEEE |
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WYV38 |
Design and minimization of reversible circuits for a data acquisition and storage system |
IEEE |
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WYV41 |
Design & implementation of mac unit using reversible logic |
IEEE |
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WYV44 |
An efficient implementation of floating point multiplier |
IEEE |
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WYV49 |
A table-based algorithm for pipelined CRC calculation |
IEEE |
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WYV69 |
Parity preserving logic based fault tolerant reversible ALU |
IEEE 2014 |
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WYV32 |
A novel analysis of sequential circuits design using reversible logic gates |
IEEE |
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WYV40 |
A distinguish between reversible and conventional logic gates |
IEEE |
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WYV42 |
Modified Toffoli gate and its applications in designing components of reversible arithmetic and logic unit |
IEEE |
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WYV43 |
A new reversible design of BCD adder |
IEEE |
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WYV45 |
Fault tolerant variable block carry skip logic (VBCSL) using parity preserving |
IEEE |
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WYV46 |
Design of a nanometric reversible 4-bit binary counter with parallel load |
IEEE |
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WYV47 |
Introduction to reversible logic gates & its application |
IEEE |
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WYV51 |
Realization of 2:4 reversible decoder and its applications |
IEEE 2014 |
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WYV52 |
All optical reversible multiplexer design using Mach-Zehnder interferometer |
IEEE 2014 |
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WYV53 |
Design of dedicated reversible quantum circuitry for square computation |
IEEE 2014 |
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WYV58 |
Energy efficient code converters using reversible logic gates |
IEEE 2014 |
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WYV59 |
Design of low logical cost conservative reversible adders using novel PCTG |
IEEE 2014 |
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WYV60 |
Contemplation of synchronous gray code counter and its variants using reversible logic gates |
IEEE 2014 |
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WYV67 |
An optimized design of binary comparator circuit in quantum computing |
IEEE 2014 |
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WYV70 |
ASIC design of reversible multiplier circuit |
IEEE 2014 |
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WYV71 |
A low energy and high performance dm^2 adder |
IEEE 2014 |
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WYV72 |
Analysis and design of a low-voltage low-power double-tail comparator |
IEEE 2014 |
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WYV73 |
Low power pulse triggered flip-flop design based on signal feed-through scheme |
IEEE 2014 |
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WYV74 |
Increase in read noise margin of single-bit-line SRAM using adiabatic change of word line voltage |
IEEE 2014 |
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WYV75 |
An 8t low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FINFETS |
IEEE 2014 |
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WYV76 |
Low power noise tolerant domino 1-bit full adder |
IEEE 2014 |
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WYV77 |
A novel low leakage and high density 5t CMOS SRAM cell in 45nm technology |
IEEE 2014 |
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WYV78 |
A new design of low power high speed hybrid CMOS full adder |
IEEE 2014 |
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WYV79 |
A low energy and high performance dm^2 adder |
IEEE 2014 |
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WYV80 |
A sub-threshold eight transistor (8T) SRAM cell design for stability improvement |
IEEE 2014 |
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WYV81 |
An arithmetic and logic unit optimized for area and power |
IEEE 2014 |
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15V61 |
Design of high performance multiply-accumulate computation unit |
IEEE 2015 |
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15V62 |
Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit |
IEEE 2015 |
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15V63 |
An approach to design a multiplexer based module of a novel reversible gate for FPGA architecture |
IEEE 2015 |
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